1. Field of the Invention
This invention relates to digital circuits, and more particularly, sequential digital circuits with multiple clock signals.
2. Description of the Related Art
Computers and other electronic systems often times require multiple clock signals for various circuits within their respective systems. In some cases, multiple clock signals may be produced from a single clock signal. One method of producing is to use a phase-locked loop (PLL). A PLL circuit (sometimes referred to as a digital locked loop, or DLL, for clock signal circuits) may receive a clock signal as an input, and produce one or more output clock signals. The frequency of the output clock signals may be a multiple of the input clock signal. Another method of producing multiple clock signals is to use a clock divider circuit. A clock divider circuit may be configured to receive an input clock signal and produce an output clock signal of a lower frequency. The output clock signal may be produced by dividing the input clock signal by a predetermined ratio. A typical clock divider circuit may include several flip-flop circuits, and may be able to divide an input clock signal by one of several even-integer ratios (e.g. 2, 4, 6, etc.).
One problem with many traditional clock circuits relates to their duty cycle. Many clock signals produced by traditional clock circuits do not have a fifty per cent duty cycle (i.e. the signal shape is asymmetrical). This may be less of a concern for low frequency systems and/or systems which use only one clock edge for triggering devices. However, some higher frequency systems may trigger some devices using the positive edge of the clock signal, while triggering other devices using the negative edge. In such systems, it may be critical for the clock signal to have a 50% duty cycle. For example, a clock signal with a 2 ns period and a 50% duty cycle, devices triggering on either clock edge have 1 ns to complete operations. However, if the clock signal is asymmetrical, have a duty cycle of 40%-60%, then devices triggering off of one clock edge may have less time to complete operations than devices triggering off the opposite clock edge. This may have a limiting effect when attempting to design systems that will utilize both clock edges for triggering devices.
Many clock divider circuits are configured primarily for dividing an input clock signal by an even-integer ratio (e.g. 2, 4, 6, etc.), as it is considered easier than dividing by an odd-integer ratio. Clock divider circuits that divide by odd-integer ratios do exist. However, these circuits are typically unable to achieve a duty cycle of 50%. Such clock circuits may be unsuitable for systems utilizing both clock edges, or where a 50% duty cycle is critical for other reasons.
The problems outlined above may in large part be solved by a clock divider circuit as described herein. In one embodiment, a clock divider circuit may include a chain of serially-coupled flip-flops. The chain may include at least a first and a second flip-flop, both of which may be triggered by a first edge of an input clock signal. A third flip-flop, coupled to (but not part of) the chain may be configured to be triggered by a second edge of the input clock signal. The third flip-flop may be coupled to an output circuit. In addition to receiving the output signal from the third flip-flop, the output circuit may also receive signals from the chain of serially-coupled flip-flops. The output circuit may drive a second clock signal, which may be produced by dividing the first clock signal based upon the signals it receives.
In one embodiment, the second clock signal may be produced by dividing the first clock signal by a predetermined ratio. The ratio by which the first clock signal is divided may be an even or odd integer, or may be a decimal ratio (e.g. 2.5). The ratio by which the first clock signal is to be divided may be determined by a selector circuit. In one embodiment, the selector circuit may be a multiplexer. The multiplexer may be configured to receive one or more selector inputs. The state of these selector inputs may determine the ratio by which the input clock signal is divided. In various embodiments, the state of the inputs to the multiplexer may be changed during the operation of the clock divider, thereby changing the ratio by which the first clock signal is divided and thus the frequency of the second clock signal.
The clock divider may be configured to provide an output clock signal that has a fifty per cent duty cycle. The input clock signal may have a fifty per cent duty cycle as well. Thus, various systems which employ the clock divider circuit may use either the positive or negative clock edge for triggering various devices within the system.
Thus, in various embodiments, the clock divider circuit may advantageously produce an output clock signal by dividing an input clock signal by a predetermined ratio. The ratio may be selectable, and may be an odd integer, an even integer, or a decimal ratio (e.g. 2.5). It should be noted that, in some embodiments, clock signals produced by dividing by a decimal ratio may not have a 50% duty cycle. The selection of the ratio by which to divide the input clock signal may be changed during operation of the clock divider circuit. The output clock signal may have a fifty per cent duty cycle, which may allow various devices in a system to be triggered by either the positive or negative edge of the output clock signal. The clock driver may be useful in computer systems that may require multiple clock signals.